How does an SSD remember things with the power off?

An SSD remembers by trapping electrons. Each flash memory cell is a transistor with an extra layer sealed inside insulating oxide. Writing uses a strong voltage to force electrons through that oxide into the layer. When the voltage goes away, nothing pushes them back out, so they stay. The trapped charge changes the voltage the cell needs to switch on, and the drive reads data by testing that voltage. The catch is that every write damages the oxide a little, and charge slowly leaks away, faster when the drive is warm. An unplugged SSD holds data for a long time, but not forever.

A transistor with a trap built in

An ordinary transistor is a switch. Put enough voltage on its gate and current flows through the channel underneath. A flash cell adds a storage layer between the gate and the channel, walled off by oxide on both sides.

A 2017 paper in the Proceedings of the IEEE by Yu Cai, Onur Mutlu and colleagues explains why that matters. The storage layer "is insulated on both sides", so the electrons stored there "do not discharge even when flash memory is powered off." That's the whole reason flash is non-volatile.

Older chips used a floating gate, a storage layer made of conductive silicon. Most of today's 3D chips use a charge trap instead. Yixin Luo's 2018 Carnegie Mellon thesis says most manufacturers now store the charge "within an insulating material", and Micron said in 2020 that it had moved from "legacy floating gate to charge-trap". The idea is the same either way. Electrons go in, and the oxide keeps them there.

Writing means tunnelling through a wall

The oxide is a barrier electrons can't climb over. So the chip doesn't make them climb. In a 2010 Samsung lecture on NAND flash, programming puts 18 volts on the control gate. The field is strong enough that electrons tunnel straight through the thin oxide, an effect called Fowler-Nordheim tunnelling.

The chip doesn't fire one big pulse. Cai's paper describes incremental step-pulse programming, which applies a short pulse, checks the cell's voltage, and repeats until the cell reaches its target.

When the pulses stop, the field is gone and the wall is just a wall again. There's nothing pushing the electrons anywhere, so they stay.

Reading only asks a question

Trapped electrons push back against the gate. A cell with more of them needs a higher gate voltage before current flows. That switch-on voltage is called the threshold voltage, and Cai's paper puts it plainly. NAND flash "stores data as the threshold voltage of each flash cell".

To read a cell, the chip applies a reference voltage set between the empty and charged levels. If current flows, the cell's threshold is below it, so the cell is empty. If no current flows, it's charged. All the other cells sharing that string get a higher pass voltage, so they conduct whatever they hold. Reading just asks the question. It doesn't rewrite the cell.

Erasing wipes a whole block

To get electrons out, the chip runs the trick in reverse. The Samsung slides show the gate at 0 volts and 20 volts on the silicon underneath, which pulls electrons back through the oxide. Cai's paper explains the side effect. All the cells in a block share that silicon, so "a flash block must be erased in its entirety".

That's why an SSD can't simply overwrite a page. Programming can only add charge, never remove it. So the drive writes new data to a fresh page, updates a map of where everything lives, and marks the old page stale. Later, it copies any still-valid pages out of a block and erases the block. Deleting a file doesn't wipe it either. The computer can send a command called TRIM, which, in the words of a 2011 USENIX paper, "informs drive that a range of LBAs is no longer in use". The old charge sits there until its block is erased. In that study, Michael Wei and colleagues at UC San Diego found an SSD holding up to 16 stale copies of some files.

More bits per cell means smaller gaps

A cell doesn't have to be just empty or charged. Fill it partway and you get more levels, all squeezed into the same voltage range. Two levels store one bit. Cai's paper lists four levels for two bits and eight for three, and Luo's thesis gives sixteen for four. Those are SLC, MLC, TLC and QLC flash.

More levels means less room between them, so the chip needs more read voltages, more careful writes, and stronger error correction. The figure below squeezes those levels into one window. The voltages and the wear are illustrative, but the level counts are real.

Pick QLC and press Let it leak. With sixteen humps and fifteen read lines, a little spreading puts cells on the wrong side of a line. SLC barely notices the same wear.

Every write wears the wall down

Tunnelling isn't gentle. Intel's application note on data retention says writing and erasing create an electric field of "more than 10 million volts per cm" across the oxide, which can damage it. The damage takes the form of broken bonds and traps, where electrons get stuck in the wrong place and leak paths form.

So each cell has a budget of program and erase cycles. Cai's paper says older SLC drives could take 150,000 cycles per cell, while 1x-nm MLC flash manages about 3,000 and TLC about 1,000. Fewer levels leave more room for a worn cell to drift.

Drives stretch that budget. The controller's wear leveling spreads writes evenly over every block, so no block wears out early, and manufacturers build in extra flash you never see, which Cai's paper calls overprovisioning. JEDEC's endurance standard, as Intel's note summarises it, turns all of this into a rating, the total terabytes a host can write before the drive stops meeting its error and retention targets.

Unplugged, the charge slowly leaks

The oxide is a very good wall, not a perfect one. Cai's paper says a 1x-nm MLC cell holds only about 100 electrons, and gaining or losing several of them can change what it reads as. Intel's note describes how electrons stuck in damaged oxide escape over time, and says this charge loss is "strongly thermally activated". Heat speeds it up a lot, and so does wear.

A powered drive fights back. Intel says the drive's internal data moves rewrite data often enough that retention during active use is "usually effectively unlimited". Then comes the catch. "Of course, such data moves are impossible when the drive is powered off."

So how long does a drive in a drawer last? JEDEC's endurance standard, as summarised in Intel's note, requires a consumer drive that has used up its rated writes to keep data for one year unpowered at 30 °C. That's a floor for a worn-out drive in a warm room. Heat and wear are what speed the leak, so a drive with writes to spare, kept cool, has more margin. In 2015 those requirements were widely misread as a sign that SSDs forget fast, and JEDEC later called the episode "an erroneous understanding of the retention data".

Still, an SSD is not an archive. If photos matter, keep more than one copy, and cloud photo storage is one way to do it.

From trapped electrons to the next question

Flash works because of error correction as much as physics. Cai's paper notes that SSD controllers rely on error-correcting codes to fix flipped bits, a cousin of the trick that keeps a damaged QR code readable. That's a good next question, and so is how electrons tunnel through a wall at all. Learnfold turns a question like that into a planned course, and every follow-up becomes a linked page, so a curiosity rabbit hole gets a map. Building a course from your own question is part of Learnfold's paid subscription. It's an AI tutor and can be wrong, so check its explanations against sources like the ones below.